ITSEN=DISABLED, ISTCLK=DISABLED, DUPLEXMD=FULL_DUPLEX, OPMD=SLAVE, CLKIDLE=IDLE_LOW, LBMD=DISABLED, CLKESEL=FALLING, DBGMD=RUN, STRTSTCLK=DISABLED, STPSTCLK=DISABLED
Module Mode Select
| DBGMD | USART Debug Mode. 0 (RUN): The USART module will continue to operate while the core is halted in debug mode. 1 (HALT): A debug breakpoint will cause the USART module to halt. Any active transmissions and receptions will complete first. |
| LBMD | Loop Back Mode. 0 (DISABLED): Loop back is disabled and the TX and RX signals are connected to the corresponding external pins. 1 (RXONLY): Receive loop back. The receiver input path is disconnected from the RX pin and internally connected to the transmitter. Data transmitted will be sent out on TX and also received by the device. 2 (TXONLY): Transmit loop back. The transmitter output path is disconnected from the TX pin and the RX input pin is internally looped back out to the TX pin. Data received at RX will be received by the device and also sent directly back out on TX. 3 (BOTH): Full loop back. Internally, the transmitter output is routed back to the receiver input. Neither the transmitter nor receiver are connected to external device pins. The device pin RX is looped back to TX in a similar fashion. Data transmitted on TX will be sent directly back in on RX. |
| STPSTCLK | Stop State Clock Control. 0 (DISABLED): When the USART is a clock master, the clock is not generated during stop bits. 1 (ENABLED): When the USART is a clock master, the clock is generated during stop bits. |
| STRTSTCLK | Start State Clock Control. 0 (DISABLED): When the USART is a clock master, the clock is held idle during a start bit. 1 (ENABLED): When the USART is a clock master, the clock is generated during a start bit. |
| ISTCLK | Idle Clock Control. 0 (DISABLED): When the USART is a clock master and CLKESEL is not equal to CLKIDLE, the clock is held idle between transmissions. When the USART is a clock master and CLKESEL equals CLKIDEL, the clock will still be generated between transmissions. When the USART is a clock slave, the USART will begin transmissions without waiting for the next clock edge. 1 (ENABLED): When the USART is a clock master, the clock is generated between transmissions or receptions. When the USART is a clock slave, the USART will wait until the next clock edge before transmitting. |
| DUPLEXMD | Duplex Mode. 0 (FULL_DUPLEX): Full-duplex mode. The transmitter and receiver can operate simultaneously. 1 (HALF_DUPLEX): Half-duplex mode. The transmitter automatically inhibits when the receiver is active and the receiver automatically inhibits when the transmitter is active. |
| CLKIDLE | Clock Idle State. 0 (IDLE_LOW): The synchronous clock is low when idle. 1 (IDLE_HIGH): The synchronous clock is high when idle. |
| CLKESEL | Clock Edge Select. 0 (FALLING): The clock falls in the middle of each bit. 1 (RISING): The clock rises in the middle of each bit. |
| ITSEN | Idle TX/UCLK Tristate Enable. 0 (DISABLED): The TX and UCLK (if in synchronous master mode) pins are always an output in this mode, even when idle. 1 (ENABLED): The TX pin is tristated when idle. If ISTCLK is cleared to 0 and the transmitter is configured in synchronous master mode, the UCLK pin will also be tristated when idle. |
| OPMD | Operational Mode. 0 (SLAVE): The USART operates as a slave. 1 (MASTER): The USART operates as a master. |